The present invention relates to electroplating both sides of a workpiece in the form of substantially flat, electrically insulative substrate having electrically interconnected circuit patterns formed on a pair of opposed major surfaces. More particularly, the present invention relates to a method for simultaneously electroplating at least one metal or metal alloy layer on electrically interconnected patterns on both surfaces of a circuit board substrate utilized for mounting and providing electrical connections to a semiconductor integrated circuit (IC) die or chip, as in ball grid array (BGA) device packages.
Electrical circuit boards and similar type components comprising complex, electrically interconnected circuit patterns formed on opposite sides of a planar, insulative substrate enjoy widespread utility in the manufacture of electrical and electronic components and devices. For example, an increasingly important aspect of semiconductor integrated circuit (IC) manufacturing technology is mounting of the semiconductor IC die or chip to an appropriately configured dual-sided substrate as part of a process for forming encapsulated device packages. Frequently, this requires providing the IC chip or die with as many input/output (xe2x80x9cI/Oxe2x80x9d) terminals as is feasible. As a consequence of the requirement for a large number of terminals to be formed on a limited amount of substrate surface, so-called xe2x80x9cball grid arrayxe2x80x9d (xe2x80x9cBGAxe2x80x9d) structures and bonding techniques have been developed in order to provide high areal density interconnections between the IC package and, e.g., a larger substrate.
A typical, encapsulated BGA type semiconductor IC device package (1) is shown in schematic, cross-sectional view in FIG. 1. According to such BGA type packaging, an IC die or chip (2) is mounted on a patterned, upper solder mask layer (3U) formed on the upper major surface (4U) of a dual-sided substrate (4), i.e., a dual-sided printed circuit board (xe2x80x9cPCBxe2x80x9d) or a ceramic or composite material circuit board (xe2x80x9cCCBxe2x80x9d) having an upper circuit pattern (5U) formed thereon. A plurality of electrical connections (6) comprising fine electrical wires, typically of gold (Au), are connected, as by wire bonding, between the upper surface (2U) of the IC die or chip (2) and a plurality of electrical bonding pad areas (7B) (also termed xe2x80x9cbond fingersxe2x80x9d) of the upper circuit pattern (5U) exposed through a plurality of openings (3xe2x80x2) selectively formed in solder mask layer (3U). Each of the electrically conductive traces or lines forming upper circuit pattern (5U) is electrically connected by means of an electrically conductive plug or via (7V) filling a through-hole (8) extending through the thickness of substrate (4), to at least one electrically conductive trace or line of a lower circuit pattern (5L) formed on the lower major surface (4L) of the substrate. A plurality of generally circularly-shaped xe2x80x9cball landxe2x80x9d areas are exposed through openings (3xe2x80x3) selectively formed in lower solder mask layer (3L) overlying substrate lower major surface (4L) for accommodating therein a spaced-apart plurality of substantially spherically-shaped electrical conductors (9) formed of a solder material and constituting a two-dimensional ball grid array (BGA). Finally, BGA package (1) includes a layer of molding material (10) encapsulating at least the IC die or chip (2).
According to BGA methodology, the device package with its substantially spherically-shaped BGA solder balls or bumps is then mated with a corresponding ball grid array (BGA) or bonding pad array formed on a substrate surface. Once mated, the solder balls or bumps of the IC device package and the corresponding solder balls or bumps or bonding pads of the substrate are heated to effect reflow and mutual bonding, whereby each solder ball or bump forms a bond between the IC device package and the substrate. As a consequence, each bonded combination functions as both an electrical and physical contact.
A variant of the above BGA bonding technology, known as xe2x80x9ccontrolled collapse chip connectionxe2x80x9d, or xe2x80x9cC4xe2x80x9d, is particularly useful in applications having a very high density of electrical interconnections. According to C4 methodology, electrically conductive balls or bumps comprising a solder material are formed on the IC device package, as well as on the mating surface of the substrate. Bonding between the two sets of solder balls or bumps is effected by application of heat and mechanical pressure to the IC device package and the substrate. The application of heat causes both sets of solder-based balls or bumps to reflow, thereby providing physical and ohmic electrical connection therebetween, while the applied mechanical pressure causes the mated pairs of solder-based balls or bumps to at least partially collapse, creating a xe2x80x9cpancakexe2x80x9d shape which advantageously reduces interconnection length and resistance.
An essential feature of the above-described BGA fabrication methodology is the formation of suitable dual-sided substrates (4) having the requisite electrically interconnected circuit patterns (5U, 5L) formed on the opposing major surfaces (4U, 4L), wherein the circuit patterns are provided with one or more plated layers for minimizing corrosion due to environmental factors, etc., and for facilitating wetting and adhesion of solder-type contact materials thereto. However, the continuing increase in complexity of the IC chip or die (2) has necessitated a parallel increase in the number of I/O connections required to be made to the IC chip or die. The increase in IC complexity has necessitated a parallel increase in the number and complexity of the requisite electrically conductive traces constituting the upper and lower circuit patterns formed on the substrate, which increase in number and complexity has in turn resulted in a substantial decrease in the inter-trace spacings.
According to conventional methodologies for manufacturing dual-sided circuit boards suitable for use in BGA type packaging applications, multi-trace electrically conductive patterns, typically of copper (Cu) or a Cu-based alloy, are formed, as by conventional techniques, on both major surfaces of a substrate comprised of at least one electrically insulative material selected from polymers, ceramics, glasses, resins, laminates, and composites thereof, e.g., an epoxy resin-fiberglass composite, and electrically interconnected by means of a plurality electrically conductive via plugs filling through-holes extending between the opposing major surfaces.
FIG. 2A illustrates, in plan view, a corner portion of the upper major surface (4U) of a first example of a dual-sided substrate (4), wherein each of the individual traces (5TU) of upper circuit pattern (5U) is shown as extending from the interior portion of upper major surface (4U), where bond fingers (7B) are located, to the periphery thereof, where conductive via plugs (7V) are formed for electrical interconnection with the lower circuit pattern (4L), which pattern is not necessarily similarly configured. The thus-formed, electrically interconnected upper and lower circuit patterns (5U, 5L) are then subjected to a plating process, conventionally electroplating, for depositing thereon a layer or layer system which provides corrosion resistance and facilitates low ohmic resistance bonding of solder-based electrical conductors thereto. Typically, thin layers of Ni and Au are sequentially electroplated over the Cu or Cu-based circuit patterns (5U, 5L) for this purpose. According to conventional electroplating processes, at least one electrically conductive tie bar (11) having several lateral extensions (11L, 11R), etc., is formed on at least one of the upper or lower major surfaces (4U or 4L) and in electrical contact with each of the conductive traces on that surface, thereby providing a common electrical conductor for connection to a source of electroplating potential, whereby each of the electrically interconnected conductive traces (5TU, 5TL) on the upper and lower major surfaces (5U, 5L), respectively, are able to be simultaneously electroplated. The electrical connections between the various conductive traces and tie bar (11) and its several extensions (11L, 11R), etc., are severed after completion of electroplating.
While the use of electrically tie bars for facilitating simultaneous electroplating of circuit patterns on opposite substrate surfaces has been generally useful according to prior practices, as a consequence of the increased densification of the traces forming the circuit patterns as required by the progressive increase in IC complexity, the remaining, or free space (or xe2x80x9creal estatexe2x80x9d) on the major surfaces (5U, 5L) of the substrate has progressively been reduced to where it currently is at a premium. Stated somewhat differently, trace densification of the circuit patterns has reached a state where the tie bar (11) and its associated extensions (11L, 11R), etc., disadvantageously and deleteriously occupy precious routing space on the substrate surface needed for the additional traces, vias, etc., required by the increased amount of I/O connections to be made to the IC chip or die. Moreover, the presence of the tie bar(s) and associated extensions disadvantageously decreases the signal-to-noise ratio (xe2x80x9cSNRxe2x80x9d) of the completed device package, and the need to sever the electrical connections between the tie bar and the conductive traces subsequent to electroplating adds additional steps and complexity to the overall substrate preparation process.
FIG. 2B illustrates, in plan view, a comer portion of the upper major surface (4U) of a second example of a dual-sided substrate (4) of conventional type, wherein each of the individual traces (5TU) of the upper circuit pattern (5U) includes a separate tie bar portion (11xe2x80x2) for supplying the electrically interconnected upper and lower circuit patterns (5U, 5L) with an electrical potential, typically of negative polarity, for cathodically electroplating thereon a layer or layer system (i.e., a plurality of stacked layers) which, inter alia, provides corrosion resistance and facilitates low ohmic resistance bonding of solder-based electrical conductors thereto. However, as in the first example illustrated in FIG. 2A, the individual tie bar portions (11xe2x80x2) of this example disadvantageously occupy precious xe2x80x9creal estatexe2x80x9d on the substrate surface, which xe2x80x9creal estatexe2x80x9d is currently at a premium due to the increased trace densification resulting from the increase in device complexity.
Accordingly, there exists a need for improved methodology for performing simultaneous electroplating of dual-sided circuit board substrates in a simple, reliable, and rapid manner, which methodology eliminates the need for providing an electrically conductive tie bar(s) and associated extensions in electrical contact with the individual conductive traces and other features constituting the conductive circuit patterns prior to electroplating, obviates the need to severing of the contacts subsequent to electroplating, and advantageously increases the SNR of the completed device package.
The present invention, wherein a multi-fingered electrical contactor is urged into simultaneous touching electrical contact with contact portions of each of the electrically conductive features comprising an electrical circuit pattern on a first one of a pair of opposed major surfaces of a substrate, facilitates and simplifies simultaneous electroplating of the first and the second electrically conductive patterns on the opposed major surfaces. The present invention therefore addresses and solves the need for improved methodology for simultaneous electroplating of at least one metal or metal alloy layer on electrically interconnected circuit patterns on both sides of a dual-sided substrate, while eliminating the need for providing and subsequently severing an electrically conductive tie bar and its associated lateral extensions. The inventive methodology thus results in process simplification while freeing precious surface area of the substrate major surfaces for use in forming additional conductive traces thereon, and advantageously increases the SNR of the completed device package. Further, the methodology provided by the present invention enjoys diverse utility in the manufacture of numerous and various types of electrical and electronic devices and/or components utilizing dual-sided circuit board substrates.
An advantage of the present invention is an improved method for simple, rapid, reliable, simultaneous electroplating of both major surfaces of printed circuit board and other types of dual-sided substrates comprising electrically interconnected conductive patterns.
Another advantage of the present invention is an improved method of simultaneously electroplating both major surfaces of dual-sided circuit board substrates utilized in fabricating ball grid array (BGA) semiconductor IC device packages.
Yet another advantage of the present invention is an improved dual-sided circuit board for use in fabricating BGA semiconductor device packages.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to one aspect of the present invention, the foregoing and other advantages are obtained in part by a method of electroplating a dual-sided workpiece, which method comprises the steps of:
(a) providing a workpiece comprising an electrically insulative substrate including first and second opposed major surfaces, with respective first and second pluralities of electrically conductive features formed on the first and the second major surfaces, each one of the first plurality of electrically conductive features on the first major surface being electrically interconnected to at least one of the second plurality of electrically conductive features on the second major surface;
(b) providing an electrical contactor in simultaneous touching electrical contact with each feature of one of the first and second pluralities of electrically conductive features; and
(c) contacting the first and second major surfaces of the substrate with at least one electroplating bath while applying an electrical potential to the electrical contactor, and simultaneously electroplating at least one layer on the first and the second pluralities of electrical features.
According to embodiments of the present invention, step (a) comprises providing as the workpiece a dual-sided circuit board comprising a substrate having flat planar first and second opposed major surfaces, wherein the first and the second pluralities of electrically conductive features each include a plurality of spaced-apart, electrically conductive traces forming respective first and second circuit patterns, and the pluralities of electrically conductive traces of the first and the second electrical circuit patterns are electrically interconnected by a plurality of electrically conductive vias extending through the thickness of the substrate.
According to various alternate embodiments of the present invention, step (a) comprises providing as the workpiece a substrate wherein the entire surface areas of each of the first and the second electrical circuit patterns are exposed; or step (a) comprises providing as the workpiece a substrate wherein the entire surface area of one the electrical circuit patterns is exposed and only selected portions of the other electrical circuit pattern are exposed through openings formed in an overlying layer of masking material; or step (a) comprises providing as the workpiece a substrate wherein only selected portions of the surface areas of each of the first and the second electrical circuit patterns are exposed through openings formed in a respective overlying layer of masking material.
According to embodiments of the present invention, step (a) comprises providing a substrate for a semiconductor device package having a ball grid array (BGA) contact arrangement, each of the layers of masking material comprises a solder mask material, and the selected portions of the first and second electrical circuit patterns exposed through the openings in the respective overlying layers of solder mask material form bonding pad areas on the first major surface and a spaced-apart array of generally circularly-shaped ball land areas on the second major surface.
According to particular embodiments of the present invention, step (a) comprises providing a substrate for a BGA contact arrangement wherein each of the generally circularly-shaped ball land areas further includes an electrical contact area extending from the periphery thereof; and step (b) comprises providing the electrical contactor in simultaneous touching electrical contact with each of the electrical contact areas of the spaced-apart array of ball land areas, wherein step (b) comprises providing as the electrical contactor an electrically conductive plate, with one end of each of a plurality of electrically conductive wires, filaments, or rods conductively affixed to one side of the plate, the plurality of conductive wires, filaments, or rods extending from the one side of the plate in a spaced-apart array configured to correspond to the spaced-apart array of ball land areas, and urging the other, free end of each wire, filament, or rod into touching electrical contact with a respective electrical contact area.
According to embodiments of the present invention, step (a) comprises providing a dual-sided circuit board comprising at least one electrically insulative material selected from the group consisting of polymers, ceramics, glasses, resins, laminates, and composites thereof; and step (c) comprises electroplating at least one metal or metal alloy layer on the first and second pluralities of electrically conductive features.
According to particular embodiments of the present invention, step (a) comprises providing a dual-sided circuit board including first and second pluralities of copper (Cu) or Cu-based features; and step (c) comprises sequentially electroplating nickel (Ni) and gold (Au) layers thereon.
According to another aspect of the present invention, a method of manufacturing an electrical device comprises:
(a) providing an electrically insulative substrate having substantially planar upper and lower major surfaces, each of the upper and the lower major surfaces including thereon a plurality of electrically conductive traces forming respective upper and lower electrical circuit patterns, the traces of the upper electrical circuit pattern being electrically interconnected with the traces of the lower electrical circuit pattern by means of electrically conductive vias extending through the substrate;
(b) applying a layer of an electrically insulative masking material on each of the upper and the lower electrical circuit patterns;
(c) selectively removing portions of each layer of masking material to expose selected surface portions of the plurality of electrically conductive traces comprising each of the upper and the lower electrical circuit patterns;
(d) providing an electrical contactor in simultaneous touching electrical contact with each selected surface portion of one of the upper and the lower electrical circuit patterns; and
(e) contacting the upper and the lower surfaces of the substrate with at least one electroplating bath and applying a cathodic electrical potential to the electrical contactor and simultaneously electroplating at least one metal or metal alloy layer on the exposed surface portions of the upper and the lower electrical circuit patterns.
According to embodiments of the present invention:
step (a) comprises providing an electrically insulative substrate comprised of a material selected from the group consisting of polymers, ceramics, glass, resins, laminates, and composites thereof;
step (b) comprises applying a layer of a solder mask material on each of the upper and the lower major surfaces of the substrate and covering the respective upper and lower electrical circuit patterns; and
step (c) comprises selectively removing portions of the solder mask layer from the upper circuit pattern to expose a plurality of electrically conductive bonding pad areas and selectively removing portions of the solder mask layer from the lower circuit pattern to expose a plurality of generally circularly-shaped ball land areas in a spaced-apart array for accommodating an array of spaced-apart, substantially spherically-shaped electrical conductors for a ball grid array (BGA).
According to particular embodiments of the present invention, step (c) includes forming an electrically conductive contact area extending from the periphery of each of the generally circularly-shaped, exposed, ball land areas of the lower circuit pattern; and step (d) comprises providing as the electrical contactor an electrically conductive plate, with one end of each of a plurality of electrically conductive wires, filaments, or rods conductively affixed to one side of the plate, the plurality of conductive wires, filaments, or rods extending from the one side of the plate in a spaced-apart array configured to correspond to the spaced-apart array of ball land areas, and urging the other, i.e., free, end of each wire, filament, or rod into touching electrical contact with a respective electrical contact area.
According to embodiments of the present invention, step (a) comprises providing a substrate wherein each of the upper and lower electrical circuit patterns includes a plurality of copper (Cu) or Cu-based traces; step (e) comprises sequentially electroplating a nickel (Ni) layer and a gold (Au) layer on each of the exposed areas of each of the upper and the lower electrical circuit patterns; and the method comprises the further steps of:
(f) affixing a substantially spherically-shaped electrical conductor to each of the plurality of exposed areas of the lower electrical circuit pattern to form a ball grid array (BGA);
(g) mounting a semiconductor integrated circuit (IC) die or chip on the layer of solder mask material on the upper major surface of the substrate;
(h) forming at least one electrical connection between the IC die or chip and at least one of the bonding pad areas of the upper electrical circuit pattern; and
(i) encapsulating at least the IC die or chip in a molding material.
According to still another aspect of the present invention, a dual-sided circuit board comprises:
an electrically insulative substrate having substantially planar upper and lower major surfaces, each of the upper and the lower major surfaces including thereon a plurality of electrically conductive traces forming respective upper and lower electrical circuit patterns, each of the traces of the upper electrical circuit pattern being electrically interconnected with the traces of the lower electrical circuit pattern by means of a plurality of electrically conductive vias extending through the thickness of the substrate; and
a layer of an electrically insulative masking material formed over each of the upper and the lower electrical circuit patterns, each of the layers of masking material including a plurality of openings extending therethrough and exposing selected surface portions of the upper and lower electrical circuit patterns, the exposed surface portions of the upper electrical circuit pattern defining a plurality of electrically conductive bonding pad areas and the exposed surface portions of the lower electrical circuit pattern defining a plurality of generally circularly-shaped, electrically conductive ball land areas in a spaced-apart array for accommodating an array of spaced-apart, substantially spherically-shaped electrical conductors for a ball grid array (BGA), wherein each of the generally circularly-shaped ball land areas further includes an electrically conductive contact area extending from the periphery thereof for facilitating electrical contact to the upper and the lower electrical circuit patterns during processing for electroplating thereon.
According to embodiments of the present invention, the electrically insulative substrate comprises a material selected from the group consisting of polymers, ceramics, glass, resins, laminates, and composites thereof; the masking material comprises a solder mask material; and each of the upper and the lower electrical circuit patterns comprises a plurality of copper (Cu) or Cu-based traces with sequentially plated nickel (Ni) and gold (Au) layers thereon.
Additional advantages and aspects of the present invention will become apparent to those skilled in the art from the following detailed description, wherein embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.